#ifndef __PINMUX_CONFIG__
#define __PINMUX_CONFIG__

/************************************************************/
/*						define								*/
/************************************************************/
/* mux selection define */
#define MUX0	0
#define MUX1	1
#define MUX2	2
#define MUX3	3

#define MUX_OK	0
#define MUX_ERR (-1)

enum
{
	READ_FROM_PIN,
	READ_FROM_GPIO
};

/************************************************************/
/*						Pinmux	setting						*/
/************************************************************/
/* UART0 PINMUX */
#define UART0_TX_MUX0	MUX0			//UART0_TX_IOB5
#define UART0_TX_MUX1	MUX1			//UART0_TX_IOC12
#define UART0_TX_MUX2	MUX2			//UART0_TX_IOC7
#define UART0_TX_MUX3	MUX3			//UART0_TX_IOA3

#define UART0_RX_MUX0	MUX0			//UART0_RX_IOB4
#define UART0_RX_MUX1	MUX1			//UART0_RX_IOC13
#define UART0_RX_MUX2	MUX2			//UART0_RX_IOC6
#define UART0_RX_MUX3	MUX3			//UART0_RX_IOA2
/* UART1 PINMUX */
#define UART1_TX_MUX0	MUX0			//UART1_TX_IOA7
#define UART1_TX_MUX1	MUX1			//UART1_TX_IOA5
#define UART1_TX_MUX2	MUX2			//UART1_TX_IOD9
#define UART1_TX_MUX3	MUX3			//UART1_TX_IOC5

#define UART1_RX_MUX0		MUX0		//UART1_RX_IOA6
#define UART1_RX_MUX1		MUX1		//UART1_RX_IOA4
#define UART1_RX_MUX_NONE	MUX2		//UART1_RX_NONE
#define UART1_RX_MUX3		MUX3		//UART1_RX_IOC4

/* EXT INTERRUPT PINMUX */
#define EXT_INT_MUX0	MUX0		//EXT_INT_A_B_C__IOC3_IOC4_IOC5
#define EXT_INT_MUX1	MUX1		//EXT_INT_A_B_C__IOC12_IOC13_IOC14
#define EXT_INT_MUX2	MUX2		//EXT_INT_A_B_C__IOA4_IOA5_IOA6
#define EXT_INT_MUX3	MUX3		//EXT_INT_A_B_C__IOB1_IOB2_IOB3

/* Timer A/B/C CCP PINMUX */
#define TIMER_CCP_MUX0	MUX0		//TIMER_A_TO_H_CCP__IOC0_IOC1_IOC2_IOC3_IOC4_IOC5_IOC6_IOC7
#define TIMER_CCP_MUX1	MUX1		//TIMER_A_TO_H_CCP__IOD2_IOD3_IOD9_IOD12_IOB2_IOB3_IOB4_IOB5
#define TIMER_CCP_MUX2	MUX2		//TIMER_A_TO_H_CCP__IOC8_IOC9_IOC10_IOC11_IOC12_IOC13_IOC14_IOC15
#define TIMER_CCP_MUX3	MUX3		//TIMER_A_TO_H_CCP__IOA0_IOA1_IOA2_IOA3_IOA4_IOA5_IOA6_IOA7

/* I2C0 PINMUX */
#define I2C0_MUX0	MUX0			//I2C0_SCL_SDA__IOB4_IOB5
#define I2C0_MUX1	MUX1			//I2C0_SCL_SDA__IOC12_IOC13
#define I2C0_MUX2	MUX2			//I2C0_SCL_SDA__IOA4_IOA5

/* I2C1 PINMUX */
#define I2C1_MUX0	MUX0			//I2C1_SCL_SDA__IOC0_IOC1
#define I2C1_MUX1	MUX1			//I2C1_SCL_SDA__IOD9_IOD12
#define I2C1_MUX2	MUX2			//I2C1_SCL_SDA__IOA6_IOA7

/* SPI0 PINMUX */
#define CS_GPIO_ENABLE	1
#define CS_GPIO_DISABLE 0

#define SPI_MUX0	MUX0			//SPI_CS_CLK_TX_RX__IOC8_IOC9_IOC10_IOC11
#define SPI_MUX1	MUX1			//SPI_CS_CLK_TX_RX__IOD0_IOD1_IOD2_IOD3
#define SPI_MUX2	MUX2			//SPI_CS_CLK_TX_RX__IOD10_IOD11_IOD12_IOD13
#define SPI_MUX3	MUX3			//SPI_CS_CLK_TX_RX__IOA6_IOA0_IOA1_IOA4
/* SPIFC PINMUX */
#define SPIFC_MUX0	MUX0			//SPIFC_CS_CLK_RX0_3__IOD0_IOD1_IOD2_IOD3_IOD4_IOD5
#define SPIFC_MUX1	MUX1			//SPIFC_CS_CLK_RX0_3__NONE

/* SDC0 PINMUX */
#define SDC0_MUX0	MUX0			//SDC0_CMD_CLK_DATA0_3__IOA2_IOA3_IOA5_IOA6_IOA7_IOA4
#define SDC0_MUX1	MUX1			//SDC0_CMD_CLK_DATA0_3__IOC6_IOC7_IOC9_IOC10_IOC11_IOC8
#define SDC0_MUX2	MUX2			//SDC0_CMD_CLK_DATA0_3__IOC0_IOC1_IOC3_IOC4_IOC5_IOC2

/* SDC1 PINMUX */
#define SDC1_MUX0	MUX0			//SDC1_CMD_CLK_DATA0_3__IOD10_IOD11_IOD13_IOC14_IOC15_IOC13
#define SDC1_MUX1	MUX1			//SDC1_CMD_CLK_DATA0_3__IODB2_IOB1_IOB3_NONE_NONE_NONE

/* TFT PIN MUX	*/
#define TFT_DATA0_7_MUX0	MUX0	//TFT_DATA_0_7__IOA0_IOA7
#define TFT_DATA0_7_MUX1	MUX1	//TFT_DATA_0_7__IOC0_IOC7

#define TFT_DATA8_15_MUX0	MUX0	//TFT_DATA_8_15__IOC0_IOC7
#define TFT_DATA8_15_MUX1	MUX1	//TFT_DATA_8_15__NONE

#define TFT_CTRL_MUX0		MUX0	//TFT_CTRL_DE_HSYNC_VSYNC_CLK__NONE_IOB1_IOB2_IOB3
#define TFT_CTRL_MUX1		MUX1	//TFT_CTRL_DE_HSYNC_VSYNC_CLK__IOC8_IOC9_IOC10_IOC11

/*	CSI PIN	MUX	*/
#define CLK_SOURCE_FROM_CSIMCLK	1
#define CLK_SOURCE_FROM_SEN2CDSP_CKO 0
#define CSI_CLKO_MUX0		MUX0	//CSI_MIPI_CLKO__IOC9
#define CSI_CLKO_MUX1		MUX1	//CSI_MIPI_CLKO__IOD9
#define CSI_CLKO_MUX2		MUX2	//CSI_MIPI_CLKO__IOD12
#define CSI_CLKO_MUX3		MUX3	//CSI_MIPI_CLKO__IOB5

#define CSI_DATA0_1_MUX1	MUX0	//CSI_DATA_0_1__IOB4_IOB5
#define CSI_DATA0_1_MUX2	MUX1	//CSI_DATA_0_1__IOC12_IOC13

#define CSI_DATA2_9_MUX0	MUX0	//CSI_DATA_2_9__IOC0_IOC7
#define CSI_DATA2_9_MUX1	MUX1	//CSI_DATA_2_9__IOC14_IOC15_IOA2_IOA7
#define CSI_DATA2_9_MUX2	MUX2	//CSI_DATA_2_9__IOC11_IOC9_IOC8_IOC10_IOB1_IOB3_IOB4_IOC13

#define CSI_CTRL_MUX0		MUX0	//CSI_CTRL_CLKI_HSYNC_VSYNC__IOC8_IOC10_IOC11
#define CSI_CTRL_MUX1		MUX1	//CSI_CTRL_CLKI_HSYNC_VSYNC__IOD10_IOD12_IOD13
#define CSI_CTRL_MUX2		MUX2	//CSI_CTRL_CLKI_HSYNC_VSYNC__IOB2_IOC14_IOC15

/*	CDSP PIN	MUX	*/
#define CDSP_CLKO_MUX0		MUX0	//CDSP_CLKO__IOC9
#define CDSP_CLKO_MUX1		MUX1	//CDSP_CLKO__IOD9
#define CDSP_CLKO_MUX2		MUX2	//CDSP_CLKO__IOD12
#define CDSP_CLKO_MUX3		MUX3	//CDSP_CLKO__IOB5

#define CDSP_DATA0_1_MUX0		MUX0	//CDSP_DATA_0_1__IOB4_IOB5
#define CDSP_DATA0_1_MUX1		MUX1	//CDSP_DATA_0_1__IOC12_IOC13
#define CDSP_DATA0_1_MUX_NONE	MUX2	//CDSP_DATA_0_1_NONE

#define CDSP_DATA2_9_MUX0	MUX0	//CDSP_DATA_2_9__IOC0_IOC7
#define CDSP_DATA2_9_MUX1	MUX1	//CDSP_DATA_2_9__IOC14_IOC15_IOA2_IOA7
#define CDSP_DATA2_9_MUX2	MUX2	//CDSP_DATA_2_9__IOC11_IOC9_IOC8_IOC10_IOB1_IOB3_IOB4_IOC13

#define CDSP_CTRL_MUX0		MUX0	//CDSP_CTRL_CLKI_HSYNC_VSYNC__IOC8_IOC10_IOC11
#define CDSP_CTRL_MUX1		MUX1	//CDSP_CTRL_CLKI_HSYNC_VSYNC__IOD10_IOD12_IOD13
#define CDSP_CTRL_MUX2		MUX2	//CDSP_CTRL_CLKI_HSYNC_VSYNC__IOB2_IOC14_IOC15

/* MIPI PIN MUX */
#define MIPI_CTRL_MUX0      MUX0	// MIPI_DATAN_DATAP_CLKN_CLKP_IOC8_10C9_IOC10_IOC11


#endif
